1. Field of the Invention
The present invention relates to circuitry implemented in complementary transistor technology that obtains an improved reliability from electric field induced failures.
2. Description of the Prior Art
In the production of integrated circuits, the reduction in the size of transistors is of great significance, in order to increase the functionality on a given semiconductor chip. However, as device geometries decrease, failure modes become apparent that were not so important at larger device sizes. For example, the "hot electron" effect has received considerable attention. This effect relates to the fact that in a field effect transistor, as the channel length decreases, the electric field in the channel increases if the operating voltage is maintained at previous levels (for example, at five volts). This increased electric field may cause the electrical carriers (i.e., holes or electrons) to gain sufficient energy as they traverse the channel to induce avalanching. When avalanching occurs, additional carriers are generated and some of these carriers may become trapped in the gate oxide region overlying the channel. These trapped charges may produce what are referred to as "fast states", which have deleterious effects on the subsequent device operation. For example, it is known that trapped charges can reduce the gain of the device, as well as change the threshold voltage; that is, the voltage between the gate and the source at which the device begins to conduct through the channel.
One remedy for degradation due to hot carriers or other electric field induced effects is simply to reduce the operating voltage on the field effect devices. However, that is not always practical. For example, in dynamic random access memories (DRAMS), it is usually desired to operate the memory portion of the circuit at a relatively high voltage in order to obtain maximum stored charge in the capacitor. At present, the nominal operating voltage for most DRAMS is five volts, plus or minus 0.5 volts. In contrast, the peripheral logic circuitry employed in the DRAMS, for example, the row and column decoders, buffers, inverters, clock circuits, etc., are desirably operated at a lower voltage (at the present state of device geometries) in order to reduce the abovenoted degradation effects. One solution has been to provide a voltage reducing circuit to provide a low voltage (e.g., 3 volts) to the logic circuits, while maintaining the full voltage (e.g., 5 volts) on the memory array. However, that limits the output swing from the integrated circuit to the lower value (e.g., 0-3 volts), which can cause problems in interfacing with other circuits designed to operate at the higher voltage.
In some cases, failure likelihood is even further increased when electric potentials exist in excess of the operating voltage. That is, a capacitor can temporarily elevate a given node above the most positive power supply voltage. For example, a "boosted node" in a clock circuit can obtain a voltage of about 7 to 8 volts for a circuit having a 5 volt power supply. An even higher voltage is possible for a double-boosted node. To discharge a boosted node to ground (0 volts), there is typically employed an n-channel MOS field effect transistor (e.g., T12 in FIG. 1). A positive clock signal (e.g., 5 volts) is applied to the gate (12) of T12 when discharge of node 10 is desired. To protect this discharge transistor, there has been employed a second transistor (e.g., T11) that drops a portion of the boosted potential. The gate (11) of the second transistor in some cases is connected to the gate (12) of the discharge transistor, or to another clock signal. In other cases, the gate (11) has been connected to the positive power supply voltage (e.g., 5 volts). The voltage thus applied to the drain of T12 (at 15) is then the voltage applied to the gate (11) of T11, minus the threshold voltage drop of T11, which is typically about 1 to 2 volts.
Another method of reducing the effects of high electric potentials is the so-called lightly doped drain structure. In that technique, the doping concentration at the drain (and typically also the source) is reduced in the vicinity of the channel, and increased away from the channel. This allows both good electrical conduct to be made to the source and drain regions while reducing the electric field in the vicinity of the channel. See for example, "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor," S. Ogura et al, IEEE Transactions on Electron Devices, Volume ED-27, pages 1359-1367 (1980). However, in some cases it is desirable to augment the protection against device degradation that the LDD structure provides. In still other cases, it is desirable to avoid the increased processing complexity that the LDD structure requires, while still providing for device protection against excessive operating fields. Furthermore, as noted above in the case of the dynamic random access memories, there are times when it is desirable to both obtain protection against excessive electric fields for certain portions of the circuit (e.g., logic portions) while providing increased operating voltages for optimum performance of other portions of the circuit (e.g., information storage cells). It is also desirable that the logic circuits be able to supply the full power supply output voltage swing (e.g., 0-5 volts).